1. Field of the Invention
This invention relates to charge pump circuits and more specifically to the output stage of a charge pump circuit which provides a stable output voltage.
2. Description of the Related Art
Charge pump circuits are often used in semiconductor circuit applications when higher voltages are required and it is desirable to avoid additional power supplies. Charge pump circuits can be used to produce higher voltages for these applications often on the same integrated circuit chip.
U.S. Pat. No. 5,625,544 to Kowshik et al. and U.S. Pat. No. 5,907,484 to Kowshik et al. describe a charge pump circuit using N stages of diode-capacitor voltage multipliers clocked to convert a low voltage to a higher voltage.
U.S. Pat. No. 5,754,476 to Caser et al. describes a negative charge pump circuit having a plurality of charge pump stages.
U.S. Pat. No. 5,877,948 to Dijkmans describes a voltage converter provided with charge pumps in which conventional rectifier diodes are replaced by output transistors.
U.S. Pat. No. 6,130,572 to Ghilardelli et al. describes a negative charge pump circuit comprising a plurality of charge pump stages connected in series.
U.S. Pat. No. 5,815,026 to Santin et al. describes an integrated circuit voltage multiplier.
U.S. Pat. No. 4,922,402 to Olivo et al. describes an integrated, multistage, CMOS voltage multiplier.
U.S. Pat. No. 5,721,509 to Taft et al. describes a charge pump having reduced threshold voltage losses.
U.S. Pat. No. 6,151,229 to Taub et al. describes a reconfigurable charge pump.
U.S. Pat. No. 6,064,251 to Park describes a low voltage charge pump system with a large output voltage range.
U.S. Pat. No. 5,635,776 to Imi describes a charge pump circuit which has a simple circuit configuration yet can boost the power source 4 or 8 times.
U.S. Pat. No. 5,489,870 to Arakawa describes a voltage booster circuit which can cancel the back bias effect, can prevent the increase of the surface area of the circuit and the power consumption, prevent the complication of the clock generation circuit, and prevent lowering of the current capability.
U.S. Pat. No. 6,023,188 to Lee et al. describes a two-phase charge pump system utilizing NMOS and/or PMOS transistors.
U.S. Pat. No. 5,877,635 to Lin describes a charge-pump circuit using a single NMOS transistor, a diode, and two capacitive means driven by a clock circuit.
U.S. Pat. No. 5,581,454 to Collins describes a DC-to-DC step-up or step-down voltage converter.
U.S. Pat. No. 5,760,637 to Wong et al. teaches a programmable charge pump producing one of a plurality of bipolar output voltages utilizing logic circuitry.
An NMOS, N channel metal oxide semiconductor field effect transistor, switch is frequently used to pass the high voltage signal from the charge pump because it is easier to control than a PMOS, P channel metal oxide semiconductor field effect transistor, switch. However, a higher voltage with better voltage regulation is required to control the gate of an NMOS switch compared to the voltage required to control the gate of a PMOS switch.
It is a principle objective of this invention to provide an output stage for a charge pump circuit which provides an increased voltage and improved voltage regulation to the gate of an NMOS switch.
It is another principle objective of this invention to provide a voltage multiplier circuit having a charge pump circuit and an output stage which provides an increased voltage and improved voltage regulation to the gate of an NMOS switch.
These objectives are achieved by inserting a diode pair between the drain of a first NMOS transistor and a first capacitor. A first NMOS transistor has its source connected to an input node and its drain connected to a second node. A second NMOS transistor has its source connected to the input node, its gate connected to the drain of the first NMOS transistor, and its drain connected to the gate of the first NMOS transistor. A second capacitor is connected between a node supplying a second clock signal and the drain of the second NMOS transistor. A second capacitor is connected between a node supplying a first clock signal and an intermediate node. A diode pair connected anode of one to the cathode of the other is inserted between the intermediate node and the drain of the first NMOS transistor. This has the effect of changing a parallel combination of capacitors to a series combination of capacitors, thereby reducing the capacitance seen by the drain of the first NMOS transistor and reducing the degradation of the output voltage.